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Tech

The CHIPS Act's Forgotten Clause: Why Arista Cashes In on Fab-Adjacent Networking

CHIPS Act subsidies build cleanrooms, but every fab campus also needs an AI-data-center-grade networking backbone for EDA simulation and automation — a toll collector nobody's pricing in.

Image: Money Racket
By at Money Racket · May 20, 2026
1-YEAR MOVE
+38% −61%
ETN ▲11.7% AVGO ▲13.8% SMCI ▼47.7%
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ETNEaton+11.7%
AVGOBroadcom+13.8%
SMCISuper Micro−47.7%

The mechanism: The CHIPS Act's $52.7 billion in subsidies and the Commerce Department's Notice of Funding Opportunity don't just underwrite cleanrooms and lithography tools — the NOFO explicitly directs applicants to build out "site development," supporting infrastructure, and supplier ecosystems around each fab. Intel's Ocotillo campus, TSMC's Fab 21 cluster in Phoenix, and Samsung's Taylor, Texas site are each effectively small cities: tens of thousands of engineers running EDA (electronic design automation) simulation farms, computational lithography, and yield-analytics clusters that behave exactly like AI data centers — thousands of GPUs/CPUs lashed together needing lossless, low-latency, high-bandwidth Ethernet fabric. Add fab automation itself — every wafer-handling robot, metrology tool, and process sensor on a leading-edge line rides a real-time industrial network — and a modern fab needs a data-center-grade backbone as a precondition for producing a single chip. Congress and Commerce get credit for "chips." The networking bill lands somewhere else entirely, and almost nobody prices it in.

Congress gets credit for "chips." The networking bill lands somewhere else entirely, and almost nobody prices it in.

Who cashes in:

  • Arista Networks ANET — the purest play. Arista's 7800R and 7050X switch families are built for exactly this workload: lossless, high-throughput Ethernet fabric for HPC/EDA simulation clusters, a market it already dominates in cloud and AI data centers. Every CHIPS-funded fab that stands up an internal simulation/compute cluster to design and tune its process node is a customer Arista never has to explain "why Ethernet" to twice.
  • Vertiv VRT — fabs and their adjacent compute halls both need industrial-grade power and thermal management for dense switch/server racks. Vertiv's UPS, cooling, and rack-power business scales directly with every new data-center-class room built alongside a fab, work that's easy to lump in under "site infrastructure" line items CHIPS applicants are required to fund.
  • Eaton ETN — same logic on the electrical-distribution side: switchgear, busway, and backup power for the networking/compute rooms that support fab operations, a category Eaton already sells heavily into hyperscale data centers and is extending into industrial/fab campuses.
  • Broadcom AVGO — supplies the merchant silicon (Tomahawk/Jericho switch ASICs) inside much of the industry's high-speed networking gear, so it collects a toll on this buildout even when a fab operator's box carries someone else's logo.

Who is exposed:

  • Super Micro SMCI — thrives on GPU-server volume, not networking-fabric revenue; a fab-adjacent compute buildout is a smaller, EDA/simulation-flavored niche where Arista's fabric and merchant switch vendors capture more of the incremental dollar than white-box server integrators do.
  • Dell DELL — competes for the compute-node business in these clusters but faces the same margin compression it sees everywhere else GPU servers have become commoditized; the fab angle doesn't change Dell's structural pricing problem.

The play: Nobody covers CHIPS Act winners past the equipment makers (Applied Materials, Lam, KLA) and the fabs themselves. The networking backbone underneath every fab campus is a quieter, recurring toll that scales with how many gigafab clusters actually get built domestically through the decade — watch Commerce's disbursement pace and each fab operator's capex commentary on compute/simulation infrastructure for confirmation this thesis is playing out.

Source: original report ↗

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