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Tech

KLA Is the Toll Booth on Every CHIPS Act Fab, and Nobody Talks About It

Samsung, TSMC, Micron, and Intel are racing each other for CHIPS Act fab dollars, but every one of their new plants has to buy the same mandatory inspection tools from KLA before it ships a qualified wafer.

Image: Money Racket
By at Money Racket · May 26, 2026

The mechanism: The CHIPS Act didn't pick a chip design winner — it funded concrete, cleanrooms, and tool-outs at Samsung Taylor, TSMC Arizona, Micron Idaho/New York, and Intel Ohio. Every one of those fabs, regardless of whose logic or memory comes out the far end, has to run wafers through process-control and inspection steps hundreds of times per lot. That's not optional tooling — foundries can't achieve yield, and can't qualify a node to a customer, without it. KLA Corporation (KLAC) sells the equipment that catches the defects: optical and e-beam wafer inspection, metrology, and reticle inspection. It holds roughly 58% share of the overall process-control market and over 85% in optical wafer inspection — a position roughly seven times its nearest competitor. Every leading-edge fab that federal subsidy dollars help build is a fab that must buy KLA tools before it ships a single qualified wafer. The chip-design horse race is genuinely uncertain; the toll booth on the track is not.

Who cashes in:

  • KLA (KLAC) — the direct and cleanest read on the thesis. Process-control intensity rises with every node shrink (KLA's own data shows 2nm requires ~90-100bps more inspection spend as a share of wafer fab equipment than 3nm), so as Samsung, TSMC, Micron, and Intel all chase sub-3nm and advanced packaging in their new U.S. fabs, KLA's dollar content per fab rises even as the four customers compete fiercely against each other.
  • Applied Materials (AMAT) and Lam Research (LRCX) — the other mandatory line items in the same fab build-outs (deposition, etch, CMP). They ride the same subsidized-construction wave, though each has more direct competition in its specific tool category than KLA does in inspection.
  • ASML (ASML) — the lithography chokepoint for EUV; every leading-edge fab needs its scanners regardless of which chip design ships, the same structural logic as KLA one layer upstream.
The chip-design horse race is genuinely uncertain; the toll booth on the track is not.

Who is exposed:

  • Intel (INTC) — a fab customer, not a fab-equipment winner here; Ohio construction delays and IDM 2.0 execution risk mean Intel absorbs capex and subsidy strings without guaranteed foundry customer wins, while its equipment suppliers get paid regardless of Intel's own outcome.
  • TSMC (TSM) and Micron (MU) as builders bear the same asymmetry: they write the capex checks and take the execution risk; the equipment layer collects the toll whether or not Arizona or Idaho fabs hit target yields on schedule.

The play: Don't bet on which chipmaker wins the subsidy race — bet on the vendor that gets paid by all of them. Watch KLA's process-control system order backlog and its "shipped but not yet installed" revenue disclosures for the actual construction-to-tool-out lag, and watch Commerce Department CHIPS disbursement milestones at commerce.gov for the next wave of fab construction that triggers KLA purchase orders.

Source: original report ↗

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